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FEATURES 14-Bit 10 MSPS A/D Converter No Missing Codes Guaranteed 3-Channel Operation Up to 10 MSPS 1-Channel Operation Up to 7 MSPS Correlated Double Sampling 1-6x Programmable Gain 300 mV Programmable Offset Input Clamp Circuitry Internal Voltage Reference Multiplexed Byte-Wide Output (8+6 Format) 3-Wire Serial Digital Interface +3/+5 V Digital I/O Compatibility 28-Lead SOIC Package Low Power CMOS: 330 mW (Typ) Power-Down Mode: <1 mW APPLICATIONS Flatbed Document Scanners Film Scanners Digital Color Copiers Multifunction Peripherals
Complete 14-Bit CCD/CIS Signal Processor AD9814
PRODUCT DESCRIPTION
The AD9814 is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of trilinear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC and Programmable Gain Amplifier (PGA), multiplexed to a high performance 14bit A/D converter. The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The 14-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface, and provide adjustment of the gain, offset, and operating mode. The AD9814 operates from a single +5 V power supply, typically consumes 330 mW of power, and is packaged in a 28-lead SOIC.
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS CML CAPT CAPB AVDD AVSS DRVDD DRVSS
VINR
CDS
PGA BANDGAP REFERENCE
AD9814
OEB
9-BIT DAC
VING
CDS
PGA
3:1 MUX
14-BIT ADC
14
14:8 MUX
8
DOUT
9-BIT DAC
CONFIGURATION REGISTER MUX REGISTER 6 RED GREEN BLUE RED GREEN BLUE DIGITAL CONTROL INTERFACE GAIN REGISTERS
VINB
CDS
PGA
SCLK SLOAD SDATA
9-BIT DAC INPUT CLAMP BIAS
OFFSET
9
OFFSET REGISTERS
CDSCLK1
CDSCLK2
ADCCLK
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD9814-SPECIFICATIONS
(TMIN to TMAX, AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS Mode, fADCCLK = 6 MHz, fCDSCLK1 = fCDSCLK2 = 2 MHz, PGA Gain = 1, Input Range = 4 V, unless otherwise noted.)
Parameter CONVERSION RATE 3-Channel Mode with CDS 1-Channel Mode with CDS ACCURACY (Entire Signal Path) ADC Resolution Integral Nonlinearity 1 (INL) INL @ 10 MHz Differential Nonlinearity (DNL) DNL @ 10 MHz No Missing Codes Guaranteed Offset Error Gain Error2 ANALOG INPUTS Input Signal Range3 Allowable Reset Transient3 Input Limits4 Input Capacitance Input Bias Current AMPLIFIERS PGA Gain at Minimum PGA Gain at Maximum PGA Resolution PGA Monotonicity Programmable Offset at Minimum Programmable Offset at Maximum Programmable Offset Resolution Programmable Offset Monotonicity NOISE AND CROSSTALK Input Referred Noise @ PGA Min Total Output Noise @ PGA Min Input Referred Noise @ PGA Max Total Output Noise @ PGA Max Channel-Channel Crosstalk POWER SUPPLY REJECTION AVDD = +5 V 0.25 V Differential VREF (@ +25C) CAPT-CAPB (4 V Input Range) CAPT-CAPB (2 V Input Range) TEMPERATURE RANGE Operating Storage POWER SUPPLIES AVDD DRVDD Total Operating Current AVDD DRVDD Power-Down Mode Current Power Dissipation Power Dissipation @ 10 MHz Power Dissipation (1-Channel Mode) 0 -65 +4.75 +3.0 +5.0 +5.0 64 1.8 150 330 355 220 Min J-Grade Typ 6 6 14 +2.5/-6.0 +4.0/-7.0 +0.6/-0.5 +0.8/-0.6 13 -12 2.2 4.0 1.0 AVSS - 0.3 10 10 1 5.8 64 Guaranteed -300 +300 512 Guaranteed 130 0.55 84 2.0 <1 0.07 2.0 1.0 +70 +150 +5.25 +5.25 1.9 0.94 0 -65 +4.75 +3.0 +5.0 +5.0 64 1.8 150 330 355 220 AVDD + 0.3 AVSS - 0.3 10 10 1 5.8 64 Guaranteed -300 +300 512 Guaranteed 130 0.55 84 2.0 <1 0.07 2.0 1.0 0.3 2.1 1.06 +70 +150 +5.25 +5.25 80 10 450 265 14 -12 2.2 4.0 1.0 AVDD + 0.3 Max 10 7 Min K-Grade Typ 6 6 14 +2.5/-6.0 +4.0/-7.0 +0.6/-0.5 +0.8/-0.6 Max 10 7 Units MSPS MSPS Bits LSB LSB LSB LSB Bits mV % FSR V p-p V V pF nA V/V V/V Steps mV mV Steps
ANALOG SPECIFICATIONS
11.0 1.0 104 5.3
V rms LSB rms V rms LSB rms LSB % FSR V V C C V V mA mA A mW mW mW
-2-
REV. 0
AD9814
NOTES 1 The Integral Nonlinearity in measured using the "fixed endpoint" method, NOT using a "best-fit" calculation. See Definitions of Specifications. 2 The Gain Error specification is dominated by the tolerance of the internal differential voltage reference. 3 Linear input signal range is from 0 V to 4 V when the CCD's reference level is clamped to 4 V by the AD9814's input clamp. A larger reset transient can be tolerated by using the 3 V clamp level instead of the nominal 4 V clamp level. Linear input signal range will be from 0 V to 3 V when using the 3 V clamp level.
4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE) 1V TYP RESET TRANSIENT 4V p-p MAX INPUT SIGNAL RANGE GND
The input limits are defined as the maximum tolerable voltage levels into the AD9814. These levels are not intended to be in the linear input range of the device. Signals beyond the input limits will turn on the overvoltage protection diodes. 5.8 5 The PGA Gain is approximately "linear in dB" and follows the equation: Gain = [ ] where G is the register value. See Figure 13. 63 - G 1 + 4.8 [ ] Specifications subject to change without notice. 63
4
DIGITAL SPECIFICATIONS C = 10 pF, unless otherwise noted.)
L
(TMIN to TMAX, AVDD = +5 V, DRVDD = +5 V, CDS Mode, fADCCLK = 6 MHz, fCDSCLK1 = fCDSCLK2 = 2 MHz,
Symbol VIH VIL IIH IIL CIN VOH VOL IOH IOL Min 2.6 0.8 10 10 10 4.5 0.1 50 50 Typ Max Units V V A A pF V V A A
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current
Specifications subject to change without notice.
TIMING SPECIFICATIONS (T
Parameter
MIN
to TMAX, AVDD = +5 V, DRVDD = +5 V)
Symbol tPRA tPRB tADCLK tC1 tC2 tC1C2 tADC2 tC2ADR tC2ADF tC2C1 tADC1 tAD fSCLK tLS tLH tDS tDH tRDV tOD tDV tHZ Min 300 140 45 20 40 0 10 10 50 50 0 Typ 500 Max Units ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns 6 16 5 3 (Fixed) ns ns ns Cycles
CLOCK PARAMETERS 3-Channel Pixel Rate 1-Channel Pixel Rate ADCCLK Pulsewidth CDSCLK1 Pulsewidth CDSCLK2 Pulsewidth CDSCLK1 Falling to CDSCLK2 Rising ADCCLK Falling to CDSCLK2 Rising CDSCLK2 Rising to ADCCLK Rising CDSCLK2 Falling to ADCCLK Falling CDSCLK2 Falling to CDSCLK1 Rising ADCCLK Falling to CDSCLK1 Rising Aperture Delay for CDS Clocks SERIAL INTERFACE Maximum SCLK Frequency SLOAD to SCLK Set-Up Time SCLK to SLOAD Hold Time SDATA to SCLK Rising Set-Up Time SCLK Rising to SDATA Hold Time SCLK Falling to SDATA Valid DATA OUTPUT Output Delay 3-State to Data Valid Output Enable High to 3-State Latency (Pipeline Delay)
Specifications subject to change without notice.
3 10 10 10 10 10 10
REV. 0
-3-
AD9814
ABSOLUTE MAXIMUM RATINGS* With Respect To AVSS AVSS AVSS DRVSS DRVSS DRVSS PIN FUNCTION DESCRIPTIONS
Parameter VIN, CAPT, CAPB Digital Inputs AVDD DRVDD AVSS Digital Outputs Junction Temperature Storage Temperature Lead Temperature (10 sec)
Min -0.3 -0.3 -0.5 -0.5 -0.3 -0.3 -65
Max AVDD + 0.3 AVDD + 0.3 +6.5 +6.5 +0.3 DRVDD + 0.3 +150 +150 +300
Units V V V V V V
Pin No. Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CDSCLK1 CDSCLK2 ADCCLK OEB DRVDD DRVSS D7 D6 D5 D4 D3 D2 D1 D0 SDATA SCLK SLOAD AVDD AVSS CAPB CAPT VINB CML VING OFFSET VINR AVSS AVDD
Type DI DI DI DI P P DO DO DO DO DO DO DO DO DI/DO DI DI P P AO AO AI AO AI AO AI P P
Description CDS Reference Level Sampling Clock CDS Data Level Sampling Clock A/D Converter Sampling Clock Output Enable, Active Low Digital Output Driver Supply Digital Output Driver Ground Data Output MSB. ADC DB13 High Byte, ADC DB5 Low Byte Data Output. ADC DB12 High Byte, ADC DB4 Low Byte Data Output. ADC DB11 High Byte, ADC DB3 Low Byte Data Output. ADC DB10 High Byte, ADC DB2 Low Byte Data Output. ADC DB9 High Byte, ADC DB1 Low Byte Data Output. ADC DB8 High Byte, ADC DB0 Low Byte Data Output. ADC DB7 High Byte, Don't Care Low Byte Data Output LSB. ADC DB6 High Byte, Don't Care Low Byte Serial Interface Data Input/Output Serial Interface Clock Input Serial Interface Load Pulse +5 V Analog Supply Analog Ground ADC Bottom Reference Voltage Decoupling ADC Top Reference Voltage Decoupling Analog Input, Blue Channel Internal Bias Level Decoupling Analog Input, Green Channel Clamp Bias Level Decoupling Analog Input, Red Channel Analog Ground +5 V Analog Supply
C C C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE
Model AD9814JR AD9814KR
Temperature Range 0C to +70C 0C to +70C
Package Description 28-Lead 300 Mil SOIC 28-Lead 300 Mil SOIC
THERMAL CHARACTERISTICS
Thermal Resistance 28-Lead 300 Mil SOIC JA = 71.4C/W JC = 23C/W
PIN CONFIGURATION
CDSCLK1 1 CDSCLK2 2 ADCCLK 3 OEB 4 DRVDD 5 DRVSS 6 (MSB) D7 7
28 AVDD 27 AVSS 26 VINR 25 OFFSET 24 VING
AD9814
23 CML
TOP VIEW 22 VINB D6 8 (Not to Scale) 21 CAPT D5 9 D4 10 D3 11 D2 12 D1 13
20 CAPB 19 AVSS 18 AVDD 17 SLOAD 16 SCLK 15 SDATA
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
(LSB) D0 14
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9814 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. 0
AD9814
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL) INPUT REFERRED NOISE
Integral nonlinearity error refers to the deviation of each individual code from a line drawn from "zero scale" through "positive full scale." The point used as "zero scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY (DNL)
The rms output noise is measured using histogram techniques. The ADC output codes' standard deviation is calculated in LSB, and converted to an equivalent voltage, using the relationship 1 LSB = 4 V/16384 = 244 mV. The noise is then referred to the input of the AD9814 by dividing by the PGA gain.
CHANNEL-TO-CHANNEL CROSSTALK
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 14-bit resolution indicates that all 16384 codes, respectively, must be present over all operating ranges.
OFFSET ERROR
In an ideal three channel system, the signal in one channel will not influence the signal level of another channel. The channelto-channel crosstalk specification is a measure of the change that occurs in one channel as the other two channels are varied. In the AD9814, one channel is grounded and the other two channels are exercised with full-scale input signals. The change in the output codes from the first channel is measured and compared with the result when all three channels are grounded. The difference is the channel-to-channel crosstalk, stated in LSB.
APERTURE DELAY
The first ADC code transition should occur at a level 1/2 LSB above the nominal zero scale voltage. The offset error is the deviation of the actual first code transition level from the ideal level.
GAIN ERROR
The last code transition should occur for an analog value 1 1/2 LSB below the nominal full-scale voltage. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions.
The aperture delay is the time delay that occurs from when a sampling edge is applied to the AD9814 until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low, so the aperture delay is measured from each clock's falling edge to the instant the actual internal sample is taken.
POWER SUPPLY REJECTION
Power Supply Rejection specifies the maximum full-scale change that occurs from the initial value when the supplies are varied over the specified limits.
REV. 0
-5-
AD9814
ANALOG INPUTS
tAD
PIXEL N (R, G, B)
PIXEL (N+1)
PIXEL (N+2)
tAD tC1
CDSCLK1
tC2C1
tPRA
tC1C2
CDSCLK2
tC2 tC2ADF
tADCLK
ADCCLK
tADC2
tC2ADR
tADC1
tADCLK
OUTPUT DATA D<7:0>
tOD
B (N-1) R (N) R (N) G (N) G (N)
R (N-2) G (N-2) G (N-2) B (N-2) B (N-2) R (N-1) R (N-1) G (N-1) G (N-1) B (N-1)
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
Figure 1. 3-Channel CDS Mode Timing
ANALOG INPUTS
tAD
PIXEL N
PIXEL (N+1)
PIXEL (N+2)
tAD tC1
CDSCLK1
tC2C1
tPRB
tC1C2
CDSCLK2
tC2 tADC1 tC2ADR tC2ADF
ADCCLK
tADCLK tADCLK tOD
PIXEL (N-3) HIGH BYTE PIXEL (N-3) LOW BYTE PIXEL (N-2) HIGH BYTE PIXEL (N-2) LOW BYTE
OUTPUT DATA D<7:0>
PIXEL (N-4) HIGH BYTE
PIXEL (N-4) LOW BYTE
Figure 2. 1-Channel CDS Mode Timing
-6-
REV. 0
AD9814
PIXEL N (R, G, B) ANALOG INPUTS PIXEL (N+1)
tAD tPRA tC2
CDSCLK2
tC2ADF tADCLK tC2ADR
tADC2
ADCCLK
tADCLK
OUTPUT DATA D<7:0>
R (N-2) G (N-2) G (N-2) B (N-2) B (N-2)
tOD
R (N-1) R (N-1) G (N-1) G (N-1) B (N-1) B (N-1) R (N) R (N) G (N) G (N)
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
Figure 3. 3-Channel SHA Mode Timing
PIXEL N ANALOG INPUTS
tAD tPRB tC2
CDSCLK2
tC2ADR tC2ADF
ADCCLK
tADCLK tADCLK tOD
PIXEL (N-3) HIGH BYTE PIXEL (N-3) LOW BYTE PIXEL (N-2) HIGH BYTE PIXEL (N-2) LOW BYTE
OUTPUT DATA D<7:0>
PIXEL (N-4) HIGH BYTE
PIXEL (N-4) LOW BYTE
Figure 4. 1-Channel SHA Mode Timing
REV. 0
-7-
AD9814
ADCCLK
tOD
OUTPUT DATA HIGH BYTE DB13-DB6 PIXEL N LOW BYTE DB5-DB0 PIXEL N
tOD
HIGH BYTE N+1 LOW BYTE N+1 LOW BYTE N+2 HIGH BYTE N+3
tHZ
tDV
OEB
Figure 5. Digital Output Data Timing
SDATA
R/Wb
A2
A1
A0
XX
XX
XX
D8
D7
D6
D5
D4
D3
D2
D1
D0
tDH
SCLK
tDS
tLS
SLOAD
tLH
Figure 6. Serial Write Operating Timing
SDATA
R/Wb
A2
A1
A0
XX
XX
XX
D8
D7
D6
D5
D4
D3
D2
D1
D0
tDH
SCLK
tDS
tRDV
tLS
SLOAD
tLH
Figure 7. Serial Read Operation Timing
-8-
REV. 0
AD9814
FUNCTIONAL DESCRIPTION
The AD9814 can be operated in four different modes: 3-Channel CDS Mode, 3-Channel SHA Mode, 1-Channel CDS Mode, and 1-Channel SHA Mode. Each mode is selected by programming the Configuration Register through the serial interface. For more detail on CDS or SHA mode operation, see the Circuit Operation section.
3-Channel CDS Mode
grounded, a zero volt input corresponds to the ADC's zero-scale output. The OFFSET pin may also be used as a coarse offset adjust pin. A voltage applied to this pin will be subtracted from the voltages applied to the red, green and blue inputs in the first amplifier stage of the AD9814. The input clamp is disabled in this mode. For more information, see the Circuit Operation section. Timing for this mode is shown in Figure 2. CDSCLK1 should be grounded in this mode. Although not required, it is recommended that the falling edge of CDSCLK2 occur coincident with or before the rising edge of ADCCLK. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is three ADCCLK cycles. The offset and gain values for the red, green and blue channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the MUX register.
1-Channel CDS Mode
In 3-Channel CDS Mode, the AD9814 simultaneously samples the red, green and blue input voltages from the CCD outputs. The sampling points for each Correlated Double Sampler (CDS) are controlled by CDSCLK1 and CDSCLK2 (see Figures 8 and 9). CDSCLK1's falling edge samples the reference level of the CCD waveform. CDSCLK2's falling edge samples the data level of the CCD waveform. Each CDS amplifier outputs the difference between the CCD's reference and data levels. Next, the output voltage of each CDS amplifier is level-shifted by an Offset DAC. The voltages are then scaled by the three Programmable Gain Amplifiers before being multiplexed through the 14-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The offset and gain values for the red, green and blue channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the MUX register. Timing for this mode is shown in Figure 1. It is recommended that the falling edge of CDSCLK2 occur coincident with or before the rising edge of ADCCLK, although this is not required to satisfy the minimum timing constraints. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is three clock cycles.
3-Channel SHA Mode
This mode operates in the same way as the 3-Channel CDS mode. The difference is that the multiplexer remains fixed in this mode, so only the channel specified in the MUX register is processed. Timing for this mode is shown in Figure 3. Although not required, it is recommended that the falling edge of CDSCLK2 occur coincident with or before the rising edge of ADCCLK.
1-Channel SHA Mode
This mode operates in the same way as the 3-Channel SHA mode, except that the multiplexer remains stationary. Only the channel specified in the MUX register is processed. The input signal is sampled with respect to the voltage applied to the OFFSET pin. With the OFFSET pin grounded, a zero volt input corresponds to the ADC's zero scale output. The OFFSET pin may also be used as a coarse offset adjust pin. A voltage applied to this pin will be subtracted from the voltages applied to the red, green and blue inputs in the first amplifier stage of the AD9814. The input clamp is disabled in this mode. For more information, see the Circuit Operation section. Timing for this mode is shown in Figure 4. CDSCLK1 should be grounded in this mode of operation. Although not required, it is recommended that the falling edge of CDSCLK2 occur coincident with or before the rising edge of ADCCLK.
In 3-Channel SHA Mode, the AD9814 simultaneously samples the red, green and blue input voltages. The sampling point is controlled by CDSCLK2. CDSCLK2's falling edge samples the input waveforms on each channel. The output voltages from the three SHAs are modified by the offset DACs and then scaled by the three PGAs. The outputs of the PGAs are then multiplexed through the 14-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The input signal is sampled with respect to the voltage applied to the OFFSET pin (see Figure 10). With the OFFSET pin
REV. 0
-9-
AD9814
INTERNAL REGISTER DESCRIPTIONS Table I. Internal Register Map
Register Name Configuration MUX Red PGA Green PGA Blue PGA Red Offset Green Offset Blue Offset
A2 0 0 0 0 1 1 1 1
Address A1 A0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
D8 0 0 0 0 0 MSB MSB MSB
D7 Input Rng RGB/BGR 0 0 0
D6 VREF Red 0 0 0
D5 Green MSB MSB MSB
Data Bits D4 CDS On Blue
D3 Clamp 0
D2 Pwr Dn 0
D1 0 0
D0 0 0 LSB LSB LSB LSB LSB LSB
3Ch/1Ch
Configuration Register
The Configuration Register controls the AD9814's operating mode and bias levels. Bits D8, D1 and D0 should always be set low. Bit D7 sets the full-scale voltage range of the AD9814's A/D converter to either 4 V (high) or 2 V (low). Bit D6 controls the internal voltage reference. If the AD9814's internal voltage reference is used, this bit is set high. Setting Bit D6 low will disable the internal voltage reference, allowing an external voltage reference to be used. Bit D5 will configure the AD9814 for either the 3-Channel (high) or 1-Channel (low) mode of operation. Setting Bit D4 high will enable the CDS mode of operation, and setting this bit low will enable the SHA mode of operation. Bit D3 sets the dc bias level of the AD9814's input clamp. This bit should always be set high for the 4 V clamp bias, unless a CCD with a reset feedthrough transient exceeding 2 V is used. If the 3 V clamp bias level is used, the peak-to-peak input signal range to the AD9814 is reduced to 3 V maximum. Bit D2 controls the power-down mode. Setting Bit D2 high will place the AD9814 into a very low power "sleep" mode. All register contents are retained while the AD9814 is in the powered-down state.
Table II. Configuration Register Settings
D8 Set to 0
D7 Input Range 1 = 4 V* 0=2V
D6 Internal VREF 1 = Enabled* 0 = Disabled
D5 # of Channels 1 = 3-Ch Mode* 0 = 1-Ch Mode
D4 CDS Operation
D3 Input Clamp Bias
D2 Power-Down
D1
D0 Set to 0
1 = CDS Mode* 1 = 4 V* 0 = SHA Mode 0 = 3 V
Set to 1 = On 0 = Off (Normal)* 0
*Power-on default value.
MUX Register
The MUX Register controls the sampling channel order in the AD9814. Bits D8, D3, D2, D1, and D0 should always be set low. Bit D7 is used when operating in 3-Channel Mode. Setting Bit D7 high will sequence the MUX to sample the red channel first, then the green channel and then the blue channel. When in this mode, the CDSCLK2 pulse always resets the MUX to sample the red channel first (see Timing Figure 1). When Bit D7 is set low, the channel order is reversed to blue first, green second and red third. The CDSCLK2 pulse will always reset the MUX to sample the blue channel first. Bits D6, D5, and D4 are used when operating in 1-Channel Mode. Bit D6 is set high to sample the red channel. Bit D5 is set high to sample the green channel. Bit D4 is set high to sample the blue channel. The MUX will remain stationary during 1-Channel Mode.
Table III. MUX Register Settings
D8 Set to 0
D7 3-Channel Select 1 = R-G-B* 0 = B-G-R
D6 1-Channel Select 1 = RED* 0 = Off
D5 1-Channel Select 1 = GREEN 0 = Off*
D4 1-Channel Select 1 = BLUE 0 = Off*
D3 Set to 0
D2 Set to 0
D1 Set to 0
D0 Set to 0
*Power-on default value.
-10-
REV. 0
AD9814
PGA Gain Registers
There are three PGA registers for individually programming the gain in the red, green and blue channels. Bits D8, D7 and D6 in each register must be set low, and bits D5 through D0 control the gain range in 64 increments. See Figure 13 for a graph of the PGA Gain versus PGA register code. The coding for the PGA registers is straight binary, with an all "zeros" word corresponding to the minimum gain setting (1x) and an all "ones" word corresponding to the maximum gain setting (5.8x).
Table IV. PGA Gain Register Settings
D8 Set to 0 0 0
D7 Set to 0 0 0
D6 Set to 0 0 0
D5 MSB 0 0
D4
D3
D2
D1
D0 LSB
Gain (V/V)
Gain (dB)
0 0
0 0 * * *
0 0
0 0
0* 1
0 0
0 0
0 0
1 1
1 1
1 1
1 1
1 1
0 1
1.0 1.013 * * * 5.4 5.8
0.0 0.12 * * * 14.6 15.25
*Power-on default value.
Offset Registers
There are three PGA registers for individually programming the offset in the red, green and blue channels. Bits D8 through D0 control the offset range from -300 mV to +300 mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as the sign bit. Table V shows the offset range as a function of the Bits D8 through D0.
Table V. Offset Register Settings
D8 MSB 0 0
D7
D6
D5
D4
D3
D2
D1
D0 LSB
Offset (mV)
0 0
0 0
0 0
0 0
0 0 * * *
0 0
0 0
0* 1
0 1 1
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0 * * *
1 0 0
1 0 0
1 0 1
1
1
1
1
1
1
1
1
1
0 +1.2 * * * +300 0 -1.2 * * * -300
*Power-on default value.
REV. 0
-11-
AD9814
CIRCUIT OPERATION
Analog Inputs--CDS Mode
Figure 8 shows the analog input configuration for the CDS mode of operation. Figure 9 shows the internal timing for the sampling switches. The CCD reference level is sampled when CDSCLK1 transitions from high to low, opening S1. The CCD data level is sampled when CDSCLK2 transitions from high to low, opening S2. S3 is then closed, generating a differential output voltage representing the difference between the two sampled levels. The input clamp is controlled by CDSCLK1. When CDSCLK1 is high, S4 closes and the internal bias voltage is connected to the analog input. The bias voltage charges the external 0.1 F input capacitor, level-shifting the CCD signal into the AD9814's input common-mode range. The time constant of the input clamp is determined by the internal 5 k resistance and the external 0.1 F input capacitance.
AD9814
CCD SIGNAL VINR CIN 0.1 F 5k CML S2 S4 OFFSET 1F + 0.1 F 4V 3V 2.2k 6.9k AVDD 1.7k INPUT CLAMP LEVEL IS SELECTED IN THE CONFIGURATION REGISTER 4pF S1 4pF CML S3
2. Linearity. Some of the input capacitance of a CMOS IC is junction capacitance, which varies nonlinearly with applied voltage. If the input coupling capacitor is too small, then the attenuation of the CCD signal will vary nonlinearly with signal level. This will degrade the system linearity performance. 3. Sampling Errors. The internal 4 pF sample capacitors have a "memory" of the previously sampled pixel. There is a charge redistribution error between CIN and the internal sample capacitors for larger pixel-to-pixel voltage swings. As the value of CIN is reduced, the resulting error in the sampled voltage will increase. With a CIN value of 0.1 F, the charge redistribution error will be less than 1 LSB for a full-scale pixel-to-pixel voltage swing.
Analog Inputs--SHA Mode
Figure 10 shows the analog input configuration for the SHA mode of operation. Figure 11 shows the internal timing for the sampling switches. The input signal is sampled when CDSCLK2 transitions from high to low, opening S1. The voltage on the OFFSET pin is also sampled on the falling edge of CDSCLK2, when S2 opens. S3 is then closed, generating a differential output voltage representing the difference between the sampled input voltage and the OFFSET voltage. The input clamp is disabled during SHA mode operation.
AD9814
VINR INPUT SIGNAL OFFSET OPTIONAL DC OFFSET (OR CONNECT TO GND) VING GREEN S2 S3 4pF S1 4pF CML RED CML
Figure 8. CDS-Mode Input Configuration (All Three Channels Are Identical)
VINB
S1, S4 CLOSED CDSCLK1 S1, S4 OPEN S2 CLOSED CDSCLK2 S2 OPEN
S1, S4 CLOSED
BLUE
S2 CLOSED
Figure 10. SHA-Mode Input Configuration (All Three Channels Are Identical)
S3 CLOSED S3 CLOSED
Q3 (INTERNAL)
S3 OPEN
S1, S2 CLOSED CDSCLK2 S1, S2 OPEN S3 CLOSED Q3 (INTERNAL) S3 OPEN
S1, S2 CLOSED
Figure 9. CDS-Mode Internal Switch Timing
External Input Coupling Capacitors
S3 CLOSED
The recommended value for the input coupling capacitors is 0.1 F. While it is possible to use a smaller capacitor, this larger value is chosen for several reasons: 1. Signal Attenuation. The input coupling capacitor creates a capacitive divider with a CMOS integrated circuit's input capacitance, attenuating the CCD signal level. CIN should be large relative to the IC's 10 pF input capacitance in order to minimize this effect.
Figure 11. SHA-Mode Internal Switch Timing
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REV. 0
AD9814
Figure 12 shows how the OFFSET pin may be used in a CIS application for coarse offset adjustment. Many CIS signals have dc offsets ranging from several hundred millivolts to more than 1 V. By connecting the appropriate dc voltage to the OFFSET pin, the CIS signal will be restored to "zero." After the large dc offset is removed, the signal can be scaled using the PGA to maximize the ADC's dynamic range.
AD9814
RED VINR SHA RED-OFFSET
3 2.0 15 6.0
12
5.0
9
4.0
6
3.0
GREEN
VING SHA GREEN-OFFSET
0 0 4 8
1.0 12 16 20 24 28 32 36 40 44 48 52 56 60 63 PGA REGISTER VALUE - Decimal
BLUE VREF FROM CIS MODULE AVDD R1 DC OFFSET R2
VINB SHA BLUE-OFFSET
Figure 13. PGA Gain Transfer Function
INL GRAPH 5.0
OFFSET 0.1 F
4.0 3.0 2.0
MAX INL +1.22 MIN INL -4.06
LSB
Figure 12. SHA-Mode Used with External DC Offset
Programmable Gain Amplifiers
1.0 0.0 -1.0 -2.0 -3.0 -4.0 -5.0 0 2000 4000 6000 8000 10000 12000 14000 16383
The AD9814 uses one Programmable Gain Amplifier (PGA) for each channel. Each PGA has a gain range from 1x (0 dB) to 5.8x (15.5 dB), adjustable in 64 steps. Figure 6 shows the PGA gain as a function of the PGA register code. Although the gain curve is approximately "linear in dB", the gain in V/V varies nonlinearly with register code, following the equation: 5.8 Gain = 63 - G 1 + 4.8 63 where G is the decimal value of the gain register contents, and varies from 0 to 63.
LSB
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0
DNL GRAPH MAX DNL +0.48 MIN DNL -0.39
0
2000
4000
6000
8000
10000 12000 14000
16383
Figure 14. Typical Linearity Performance
REV. 0
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GAIN - V/V ( )
GAIN - dB ( )
AD9814
APPLICATIONS INFORMATION Circuit and Layout Recommendations
The recommended circuit configuration for 3-Channel CDS mode operation is shown in Figure 15. The recommended input coupling capacitor value is 0.1 F (see Circuit Operation section for more details). A single ground plane is recommended for the AD9814. A separate power supply may be used for DRVDD, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as the rest of the AD9814. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC, or by using external digital buffers. To minimize the effect of digital transients during major output code transitions, the falling edge of CDSCLK2
should occur coincident with or before the rising edge of ADCCLK (see Figures 1 through 4 for timing). All 0.1 F decoupling capacitors should be located as close as possible to the AD9814 pins. When operating in single channel mode, the unused analog inputs should be grounded. Figure 16 shows the recommended circuit configuration for 3Channel SHA mode. All of the above considerations also apply for this configuration, except that the analog input signals are directly connected to the AD9814 without the use of coupling capacitors. The analog input signals must already be dc-biased between 0 V and 4 V (see the Circuit Operation section for more details).
+5V CLOCK INPUTS 3
1 2
0.1 F RED INPUT 0.1 F 0.1 F 0.1 F BLUE INPUT GREEN INPUT
CDSCLK1 CDSCLK2 ADCCLK OEB DRVDD DRVSS
AVDD 28 AVSS 27 VINR 26 OFFSET 25
+5V/3V
3 4 5
0.1 F
6 7 8 9 10 11 12 13 14
AD9814
VING 24 CML 23 VINB 22 CAPT 21 CAPB 20 AVSS 19 AVDD 18 SLOAD 17 SCLK 16 SDATA 15 3
0.1 F
0.1 F 0.1 F
1.0 F
D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB)
0.1 F
+
10 F 0.1 F
0.1 F
+5V
DATA OUTPUTS
8
SERIAL INTERFACE
Figure 15. Recommended Circuit Configuration, 3-Channel CDS Mode
+5V CLOCK INPUTS 3
1 2
RED INPUT 0.1 F GREEN INPUT BLUE INPUT
CDSCLK1 CDSCLK2 ADCCLK OEB DRVDD DRVSS
AVDD 28 AVSS 27 VINR 26 OFFSET 25
+5V/3V
3 4 5
0.1 F
6 7 8 9 10 11 12 13 14
AD9814
VING 24 CML 23 VINB 22 CAPT 21 CAPB 20 AVSS 19 AVDD 18 SLOAD 17 SCLK 16 SDATA 15 3
0.1 F 0.1 F 0.1 F + 10 F 0.1 F
D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB)
0.1 F
+5V
DATA OUTPUTS
8
SERIAL INTERFACE
Figure 16. Recommended Circuit Configuration, 3-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground)
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REV. 0
AD9814
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead, 300 Mil SOIC (R-28)
C3616-2.5-7/99
45 0.0500 (1.27) 0.0157 (0.40) 0.7125 (18.10) 0.6969 (17.70)
28
15
0.2992 (7.60) 0.2914 (7.40)
1 14
0.4193 (10.65) 0.3937 (10.00)
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0 0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
REV. 0
-15-
PRINTED IN U.S.A.

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